1. Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to form portions of a device on an insulator layer without forming a floating body device.
2. Description of Prior Art
Devices formed in silicon layers which in turn completely overlying insulator, have allowed reductions in performance degrading parasitic capacitances to be realized. The increased performance of devices fabricated using silicon on insulator (SOI), technology however is achieved at higher processing costs when compared to counterpart devices formed in, and only overlying, semiconductor material. The increased cost of SOI devices is attributed to the additional processing used to form the SOI layer, with a first option featuring bonding procedures, where one of the bonded wafers features the insulator layer, followed by thinning of the bonded semiconductor wafer. A second option, also resulting in increased processing cost, is formation of the SOI layer via implantation of oxygen ions into a semiconductor wafer followed by an anneal cycle resulting in an silicon oxide layer located underlying a thin portion of unimplanted silicon. In addition to the increased processing costs incurred with the SOI technology, the presence of an insulator layer on the entire surface of the semiconductor can result in a floating body effect, wherein the semiconductor substrate is floating with respect to the device channel region. This can result in unwanted threshold voltages thus adversely influencing designed operating conditions.
This invention will describe a method of fabricating a device where only portions of the device overlay insulator layer, wherein the overlaid insulator layer is buried oxide regions, not an entire insulator layer as is the case with SOI layers. The use of buried oxide regions still allow decreased parasitic capacitance and increased performance to be realized, without experiencing the negative device parameters encountered with SOI, floating body type devices. Prior art such as Chu et al, in U.S. Pat. No. 6,251,751 B1, Juengling, in U.S. Pat. No. 5,670,412, Huang, in U.S. Pat. No. 6,235,567 B1, and Chu et al, in U.S. Pat. No. 5,963,817, describe methods of forming buried oxide regions, however none of these prior art describe the unique combination of process steps of this present invention, allowing optimum buried oxide regions to be formed and overlaid by specific portions of a semiconductor device.